1. Field of the Invention
The present invention relates generally to a read only memory based in semiconductor technology having a vertical MOS transistor.
2. Description of the Related Art
Memories into which data are written permanently in a digital form are required for many electronic systems. Such memories are called, inter alia, read-only-memories.
Plastic disks which are coated with aluminium are in widespread use as read-only-memories for storing very large quantities of data. These plastic disks have two different kinds of point-like depressions in the aluminum coating, which are assigned to the logic values zero and one. The information is stored digitally in the arrangement of these depressions. Such disks are called compact disks, or CDs, and are in widespread use for the digital storage of music.
In order to read the data which are stored on a compact disk, a read apparatus is used in which the disk rotates mechanically. The point-like depressions are scanned via a laser diode and a photo cell. Typical scanning rates in this case are 2.times.40 kHz. 4 GBits of information can be stored on one plastic compact disk.
The read apparatus has moving parts which are subject to mechanical wear, occupy a comparatively large spaces and allow only slow data access. Furthermore, the read apparatus is sensitive to vibration and can thus be used only to a limited extent in mobile systems.
Read-only-memories based on semiconductor technology are known for the storage of smaller quantities of data. These are widely implemented as a planar integrated silicon circuit, in which MOS transistors are used. The transistors are selected via the gate electrode, which is connected to the word line. The input of the MOS transistor is connected to a reference line, and the output to a bit line. An assessment is carried out during the reading process to determine whether any current is or is not flowing through the transistor. The logic values zero and one are assigned accordingly. Technically, the storage of logical zero and one values brought about in that no MOS transistor is produced or no conductive connection to the bit line is implemented in memory cells in which the logic value assigned to the state "no current flow through the transistor" is stored. Alternatively, MOS transistors which have different operating voltages as a result of different implantations in the channel region can be implemented for the two logic values.
These memories based on semiconductor technology allow random access to the stored information. The electrical power which is required to read the information from the semiconductor memory is considerably less than in the case of a read apparatus having a mechanical drive. Since no mechanical drive is required to read the information, the problems of mechanical wear and the sensitivity to vibration are illuminated. Read-only-memories based on a semiconductor technology can thus also be used for mobile systems.
The silicon memories described have a planar construction. As a consequence, a minimal surface area, which is about 6 to 8 F.sup.2, is required per memory cell, F being the smallest producible structure size in the respective technology. Planar silicon memories are thus limited to memory densities of about 0.14 bit/.mu.m.sup.2 when using one-.mu.m technology.
U.S. Pat. No. 4,954,854 discloses the use of vertical MOS transistors in a read-only-memory. The surface of a silicon substrate is for this purpose provided with trenches against which a source region abuts at the base, against which a drain region abuts at the substrate surface and along whose flanks a channel region is arranged. The surface of the trench is provided with a gate dielectric, and the trench is filled with a gate electrode. Logical zero and one values are distinguished in this arrangement by no trench being etched and no transistor being produced for one of-the logic values.
German Patent Document DE 42 14 923 A1 discloses a read-only-memory cell arrangement whose memory cells comprise MOS transistors. These MOS transistors are arranged along trenches such that a source region abuts the base of the trench, a drain region abuts the surface of the substrate, and a channel region abuts the flank and base of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a flank covering or (spacer). The logic values zero and one are distinguished by different operating voltages, which are brought about by channel implantation. During the channel implantation, the ions being implanted strike the surfaces of the respective trench at such an angle that implantation is carried out, deliberately, along only one flank as a result of shadowing effects of the opposite flank.